http://www.linux-mag.com/id/4610/ Open Source, Open Standards Sat, 05 Oct 2013 13:48:18 +0000 hourly 1 http://wordpress.org/?v=3.1 http://www.linux-mag.com/id/4610/#comment-4927 tgawne Wed, 30 Nov -0001 00:00:00 +0000 http://www.linux-mag.com/id/4610/#comment-4927 I have thought about this as AMD and Intel have put there quad core solutions out. I was under the wrong impression that when go from one to two to 4 cores that you would see a basic 4 fold rise in performance. After discussing this with our HPC folks here at the lab I was corrected. So my question is then how could you get a four fold increase using four cores? Where is the bottle neck? I have thought about this as AMD and Intel have put there quad core solutions out. I was under the wrong impression that when go from one to two to 4 cores that you would see a basic 4 fold rise in performance. After discussing this with our HPC folks here at the lab I was corrected. So my question is then how could you get a four fold increase using four cores? Where is the bottle neck?

]]> http://www.linux-mag.com/id/4610/#comment-4928 deadline Wed, 30 Nov -0001 00:00:00 +0000 http://www.linux-mag.com/id/4610/#comment-4928 The simple answer is "it all depends on the application." The longer answer is contention for resources which in most cases is memory. Both Intel<br /> and AMD solve this in different ways right now,<br /> although Intel is moving toward the method used<br /> by AMD -- a fast memory sharing bus called hyperchannel. Think of it this way, before multi-core, processors were much faster than memory (which is why cache memory is used), but now you have more cores hitting the same memory. In some cases codes can run well in others there is a bottleneck, which leads back to my first short answer. The simple answer is “it all depends on the application.” The longer answer is contention for resources which in most cases is memory. Both Intel
and AMD solve this in different ways right now,
although Intel is moving toward the method used
by AMD — a fast memory sharing bus called hyperchannel. Think of it this way, before multi-core, processors were much faster than memory (which is why cache memory is used), but now you have more cores hitting the same memory. In some cases codes can run well in others there is a bottleneck, which leads back to my first short answer.

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